Magnetic QCA

home | teaching | research | publications | service

• Project Goal:
  • Magnetic logic based on ferrite cores was pursued in the 1950s, but due to disadvantages such as bulk, was replaced by semiconductor technology. I am studying systems made from nanomagnets that (i) are scalable, (ii) do not possess the disadvantages of the early, bulky, ferrite core magnets, and (iii) can be arranged to form circuits within the quantum-dot cellular automata (QCA) architecture scheme. For nanomagnet-based QCA (MQCA), wires, gates, and inverters have all been experimentally realized and verified, they operate at room temperature, and it is estimated that if 10¹⁰ magnets switch 10⁸ times/second, they would only dissipate about 0.1 W of power. When the drive circuitry is considered, power budgets remain low and could better CMOS equivalents by several orders of magnitude.
  
  
• Research Activities:
  1. Design and evaluate clock structures: A lithographically-defined clock structure is used to generate a magnetic field that polarizes groups of nanomagnets along their hard axes and removes the remanent magnetizations associated with a previous computation. When the field is removed, magnets relax to their new preferred state in response to new inputs. My group is continuing to (a) fabricate and test the clock wires, (b) measure their power/performance, and (c) design necessary clock generation circuitry.
  
  
  2. Expand the "parts library": For MQCA, all of the components needed for a functionally complete logic set have been experimentally verified. However, more than gates and inverters are required to build circuits. Structures that allow signals to turn corners, cross, and fan-out must also be designed and verified. By varying a magnet’s shape, my group has developed structures that should facilitate these tasks and we have verified designs with a NIST-developed, physical-level simulator. We will continue to follow this path to (a) ensure structures are robust against fabrication variation and (b) develop a CAD flow well grounded in the correct device physics in order to more readily consider larger designs.
  
  
  3. Evaluate systems-level performance: Circuit components that only work in isolation are ultimately insufficient. A meaningful evaluation of an emerging technology should show that circuit components could be integrated into systems-level structures that are capable of performing a computationally interesting task better than the projected state of the art for CMOS. We are evaluating three systems-level architectures assuming an MQCA implementation: (a) a reconfigurable PLA, (b) systolic architectures for signal processing, and (c) integration of nanomagnets with MRAM to more easily facilitate processing-in-memory. We will compare our designs to CMOS and other emerging technologies.
  
  
  4. Experimentally verify core components: To meaningfully verify projected systems-level performance, even physical-level simulations are insufficient. Thus, we are working to fabricate arrangements of nanomagnets that facilitate (a) wire crossings, (b) fan-out, and (c) fan-in. We will also attempt to experimentally demonstrate the core of our PLA design (a circuit that consists of ~20 nanomagnets). Experimental results will be compared to simulation data.

Quilt Packaging

• Project Goal:
  • "Quilt Packaging" (QP) allows contiguous tiling of ICs in two dimensions with gaps between chips of only a few microns, leading to ultrahigh-bandwidth signal transmission between chips, plus lower power dissipation, higher silicon efficiency, lower system weight and volume, at less cost and with good prospects for improved interconnect reliability. Quilt Packaging is promising, fundamentally simple, and practical. QP employs a multitude of short, conductive nodules that protrude horizontally from the side, vertical facets of ICs to interconnect the various ICs of a system, resulting in an array of chips that we call a "quilt." These nodules have been fabricated at Notre Dame in widths ranging from 10 to 100 microns. Assuming that nodules of at least 5 microns are practical, a 15 mm chip would be able to make up to 1,500 superconnects per edge to adjacent die. This has extreme implications for greatly improving system performance while at the same time simplifying expensive and power/area-inefficient wiring board materials.
  
  
• Research Activities:
  1. Identify architectural configurations of interest that are enabled or enhanced by Quilt Packaging.
  
  
  2. Leverage QP to integrate heterogeneous technologies to enable performance wins.
  
  
  3. Utilize the Structural Simulation Toolkit (SST) to evaluate the performance of these architectures.
  
  
  4. Identify future simulation and fabrication experiments that will demonstrate QP architectures.
  
  
  5. Compare and contrast to the "state of the art" including Sun Microsystem’s "Proximity Communication," in which die are stacked at edges and communicate capacitively, SiliconPipe’s "Off-the-Top" technology, in which microwave-guides supported above the printed wiring board (PWB) connect packages, and 3D chip-stacking, in which die are thinned and stacked directly, using microvias or wirebonds to make connections between levels.
  
  

Molecular Electronics

• Project Goal:
  • Molecular Quantum-dot Cellular Automata (QCA) devices could overcome several performance obstacles that nano-scale transistors cannot. Potential performance wins include lower latencies, higher device densities, scalable interconnect, and lower power dissipation. I am working to determine what applications are well suited for molecular QCA and if the required infrastructure could feasibly be built.
  
  
• Research Activities:
  1. Studying feasibility of a self-assembly fabrication process for defect tolerant circuit components using: (a) covalently bonded square arrays of two ferrocenium and two ferrocene complexes as devices, (b) DNA tiles as a circuitboard (Seeman/Winfree rafts or Rothemund's "DNA Origami"), (c) Electron beam lithography etched silicon coated with a cationic adhesion layer as a substrate.
  
  
  2. Evaluating whether efficient application architectures are possible given the above fabrication process. Our design targets are currently (a) digital signal processing, (b) general purpose processing, and (c) simple nodes for supercomputers.
  
  
  3. Benchmarking potential circuits and architectures against the projected state of the art for silicon-CMOS as well as other emerging technologies, specifically: systems of carbon nanotubes, silicon nanowires, quantum logic, and orientation-based technologies.