teaching | research | publications | service
Michael T. Niemier(mniemier@nd.edu)
380 Fitzpatrick Hall
Notre Dame, IN 46556
(574) 631-3858
Dropbox
Research
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Nanomagnet Logic (NML)
- Computing with nanoscale magnets
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Quilt Packaging
- (Integrating heterogenous technologies in the same package)
Research Support
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Radiation-Hard Nanomagnetic Logic with Electronic Input and Output
- Department of the Navy
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Characterization of and I/O for Magnetic Logic Structures
- National Science Foundation
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Benchmarking Emerging Technologies: Looking Up to Applications
- IBM
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Blending Processing into Advanced Memory Technologies to Enhance Massive, Memory-critical Applications
- Department of Defense
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Midwest Institute for Nanoelectronics Discovery
- SRC NRI
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Applications, Architectures, and Circuit Design for Nano-scale Magnetic Logic Devices
- National Science Foundation
Teaching
- Fall 2009 - Computer Architecture I (CSE 30321)
- Spring 2009 - Computing at the Nanoscale (CSE 40547/60547)
Students
- Current graduate students I advise or co-advise:
- Tanvir Alam (EE) -- NML Clock Structures
- Aaron Dingler (CSE) -- NML Circuit Design and Simulation
- Steve Kurtz (CSE) -- NML Circuit Design and Simulation
- M. Siddiq (EE) -- NML Circuit and I/O Fabrication
- Other graduate students I work with:
- Michael Crocker (CSE) -- Reconfigurable and Systolic NML Architectures
- Shawn Liu (CSE) -- Electrical Interface to NML + Experimental/Simulation Correlation
- Peng Li (EE) -- Magnetic Measurements + Electrical Interface to NML Fabrication
- Edit Varga (EE) -- NML Circuit Fabrication
- Current Undergraduate Students:
- Evan Lent (NML Circuit Simulation)
- Samuel Lopes (NML Circuit Simulation)
- Dane Peters (NML Circuit Simulation)
Recent Publications
Copies of papers are provided for your personal use
to ensure timely dissemination of scholarly work. Redistribution is prohibited. All rights
are retained by copyright holders.
- A. Dingler, M.J. Siddiq, M.T. Niemier, X.S. Hu, M.T. Alam, G.H. Bernstein, and W. Porod, "Controlling Magnetic Circuits: How Clock Structure Implementation will Impact Logical Correctness and Power," in Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, p.94-102, October 7-9, 2009.
- A. Dingler, M.T. Niemier, X.S. Hu, M.T. Alam, and M. Garrison, "System-Level Energy and Performance Projections for Nanomagnet-based Logic," in Proceedings of the IEEE Symposium on Nanoscale Architectures, p.21-26, July 30-31, 2009 (Best Paper Award).
- E. Varga, M. T. Niemier, G.H. Bernstein, W. Porod, and X. Sharon Hu, "Non-volatile and Reprogrammable MQCA-based Majority Gates," in Proceedings of the Device Research Conference, June 22, 2009.
Conferences
- A list of conferences relevant to our group's research can be found here.
