Education

• Ph.D. Electrical Engineering, Stanford University, Jan. 1973
• M.S Systems & Engineering Sciences, Syracuse University, Aug. 1970
• B.S. Electrical Engineering, University of Notre Dame, 1968

Vitae

Dr. Kogge was with IBM, Federal Systems Division, from 1968 until 1994, and was appointed an IEEE Fellow in 1990, and an IBM Fellow in 1993. In 1977 he was a Visiting Professor in the ECE Dept. at the University of Massachusetts, Amherst. From 1977 through 1994, he was also an Adjunct Professor in the Computer Science Dept. of the State University of New York at Binghamton. In August, 1994 he joined the University of Notre Dame as first holder of the endowed McCourtney Chair in Computer Science and Engineering (CSE). Starting in the summer of 1997, he has been a Distinguished Visiting Scientist at the Center for Integrated Space Microsystems at JPL. He is also the Research Thrust Leader for Architecture in Notre Dame's Center for Nano Science and Technology. For the 2000-2001 academic year he was the Interim Schubmehl-Prein Chairman of the CSE Dept. at Notre Dame. From August, 2001 until Dec. 2008 he was the Associate Dean for Research, College of Engineering. Starting in the fall of 2003, he also has been a Concurrent Professor of Electrical Engineering.

Research Interests

His current research areas include massively parallel processing architectures, advanced VLSI and nano technologies and their relationship to computing systems architectures, non von Neumann models of programming and execution, parallel algorithms and applications, and their impact on computer architecture. Since the late 1980s' this has focused on scalable single VLSI chip designs integrating both dense memory and logic into "Processing In Memory" (PIM) architectures, efficient execution models to support them, and scaling multiple chips to complete systems. This includes not only efficient parallel processing topologies, control strategies, and chip floor plans, but doing so with inherently low power CPU architectures, and for a range of real system applications from highly scalable deep space exploration to exa-scale level supercomputing. Special emphasis has been on alternative models of massive light and ultra-light weight multi-threading.

Other recent work has focused on how PIM-like ideas may port into nanotechnology such as quantum dot cellular array (QCA), where instead of "Processing-In-Memory" we have opportunities for "Processing-In-Wire" and similar paradigm shifts. A key part of this is focusing on the interchange between the underlying device physics, the design rules and metaphors best suited to using such devices, and how to recast "conventional" computing structures into such design metaphors in ways that optimize the overall system.

Accomplishments

Most recently, Dr. Kogge led a DARPA-sponsored group of industry and academic technical experts in developing a detailed projection of the technical challenges needed to advance the art of supercomputing to the exascale level (1000 times today's emerging petascale computers). Both a report and an IEEE radio interview are available.

Since coming to Notre Dame, Dr. Kogge has participated on a long series of projects aimed at achieving new levels of supercomputing performance by leveraging both technology and architecture. This includes proposing one of the three "petascale" architectures that emerged from the "Enabling Technologies for Petascale Computing" workshop, held in Feb. of 1994. These PIM-based concepts were developed through a long series of petascale development projects including HTMT and Cray's Cascade project, and in collaboration with Dr. Jay Brockman, PIM LITE - one of the first real chips architected to have processing next to memory. The work with Cray led to multiple patents on light weight and ultra light weight multi-threading, the latter including conversion of traditional memory references into "traveling threads."

Earlier work with a student of his Victor Zyuban (now at IBM) led to one of the first in-depth studies of an alternative superscalar microarchitecture that would support far better energy-performance characteristics than conventional out-of-order execution.

While at IBM one of his groups designed the first multi-processor PIM device with significant DRAM memory, that may also arguably be the world’s first multi-core chip. This EXECUBE chip integrated 4 Mbits of DRAM with over 100K gates of logic to support on a single chip a complete 8-core binary hypercube parallel processor which could run in both SIMD and MIMD modes, and a paper on its architecture received the Daniel Slotnick Award at the 1994 Int. Conf. on Parallel Processing. He also designed and built the RTAIS parallel processor which demonstrated a pure SIMD PIM-like architecture optimized for supporting a LINDA-like parallel processing model, with real time scheduling included. Prior parallel machines included the IBM 3838 Array Processor which for a time was the fastest single precision floating point processor marketed by IBM, and the Space Shuttle Input/Output Processor which has flown on every Shuttle mission, and probably represents the first true parallel processor to fly in space. The IOP also represents one of the earliest examples of multi-threaded architectures.

His Ph.D. thesis on the parallel solution of recurrence equations was one of the early works on what is now called parallel prefix operations, and applications of those results are still acknowledged as defining the fastest possible implementations of circuits such as adders with limited fan-in logic (known as the Kogge-Stone adder). His 1982 book, “The Architecture of Pipelined Computers” is widely regarded as perhaps the first formal treatise on this now-ubiquitous technique.