Education

Vitae

Dr. Kogge was with IBM, Federal Systems Division, from 1968 until 1994, and was appointed an IEEE Fellow in 1990, and an IBM Fellow in 1993. In 1977 he was a Visiting Professor in the ECE Dept. at the University of Massachusetts, Amherst. From 1977 through 1994, he was also an Adjunct Professor in the Computer Science Dept. of the State University of New York at Binghamton. In August, 1994 he joined the University of Notre Dame as first holder of the endowed McCourtney Chair in Computer Science and Engineering (CSE). Starting in the summer of 1997, he has been a Distinguished Visiting Scientist at the Center for Integrated Space Microsystems at JPL. He is also the Research Thrust Leader for Architecture in Notre Dame's Center for Nano Science and Technology. For the 2000-2001 academic year he was the Interim Schubmehl-Prein Chairman of the CSE Dept. at Notre Dame. Starting in August, 2001 he is the Associate Dean for Research, College of Engineering. Starting in the fall of 2003, he also is a Concurrent Professor of Electrical Engineering.

Research Interests

His current research areas include massively parallel processing architectures, advanced VLSI and nano technologies and their relationship to computing systems architectures, non von Neumann models of programming and execution, parallel algorithms and applications, and their impact on computer architecture. Since the late 1980s' this has focused on scalable single VLSI chip designs integrating both dense memory and logic into "Processing In Memory" (PIM) architectures, efficient execution models to support them, and scaling multiple chips to complete systems. This includes not only efficient parallel processing topologies, control strategies, and chip floor plans, but doing so with inherently low power CPU architectures, and for a range of real system applications, from highly scalable deep space exploration to trans-petaflops level supercomputing.

More recent work is investigating how PIM-like ideas may port into quantum cellular array (QCA) and other nanotechnology logic, where instead of "Processing-In-Memory" we have opportunities for "Processing-In-Wire" and similar paradigm shifts. A key part of this is focusing on the interchange between the underlying device physics, the design rules and metaphors best suited to using such devices, and how to recast "conventional" computing structures into such design methaphors in ways that optimize the overall system. One example of the former is developoment of an FPGA-like basic cell that is well-suited to QCA. An example of the latter is development of a very dense memory model optimized for future QCA devices at the molecular level where there is a recursive rather than array framework to the memory, and where there is no longer a separate "CPU," just traveling "memory requests" that have grown into complete light weight threads.

Prior Accomplishments

While at IBM one of his groups designed the first multi-processor PIM device with significant DRAM memory. This EXECUBE chip integrated 4 Mbits of DRAM with over 100K gates of logic to summport on a single chip a complete 8 way binary hypercube parallel processor which could run in both SIMD and MIMD modes. He also designed and built the RTAIS parallel processor which demonstrated a pure SIMD PIM-like architecture optimized for supporting a LINDA-like parallel processing model, with real time scheduling included. Prior parallel machines included the IBM 3838 Array Processor which for a time was the fastest single precision floating point processor marketed by IBM, and the Space Shuttle Input/Output Processor which has flown on every Shuttle mission, and probably represents the first true parallel processor to fly in space. The IOPalso represents one of the earliest examples of multi-threaded architectures. His Ph.D. thesis on the parallel solution of recurrence equations was one of the early works on what is now called parallel prefix operations, and applications of those results are still acknowledged as defining the fastest possible implementations of circuits such as adders with limited fan-in blocks (known as the Kogge-Stone adder).