Journals, Refereed Conferences and Workshop Publications by
Peter M. Kogge:
Journals
- Murphy, Richard C. and Peter
M. Kogge, “On the Memory Access Patterns of Supercomputer
Applications: Benchmark Selection and its Implications,” IEEE Trans.
on Computers, Vol. 56, Issue 7, July 2007, 937-945.
- D. Z. Chen, O. Daescu, Journal Hershberger, P. M. Kogge, N. Mi, S. Snoeyink, "Polygonal Path Approximation with
Angle Constraints," Computational Geometry: Theory and Applications,
Vol. 32, No. 3, 2005, pp. 173-187.
- Dmitry
Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose, Peter Kogge,
"Energy-Efficient Issue Queue Design," IEEE Trans. on Very Large
Scale Integration Systems, vol. 11, No. 5, Oct. 2003, pp. 789-800.
- Zyuban,
Victor and Peter M. Kogge, "Inherently Lower-Power High-Performance
Superscalar Architectures," IEEE Trans. on Computers, March 2001, pp.
268-285.
- Niemier, Michael T. and Peter
M. Kogge, "Problems in designing with QCAs:
Layout = Timing," Int. Journal of Circuit Theory and Applications, 4 January 2001, Vol. 29, Portland,
OR, Nov. 1999, pp. 49-62.
- Ghose, Kanad, Kiran R. Desai, Peter M. Kogge. "Accelerating
object-oriented applications using method lookup caches and register
windowing," Journal of Systems Architecture, Vol. 45, 1999, pp.
1023-1046.
- Zyuban,
Victor and Peter M. Kogge, "Application of STD Method to Latch Power
Estimates," IEEE Trans. on VLSI Systems, Vol. 7, No. 1, March 1999,
pp. 111-115
- T. Sunaga, Peter M. Kogge, et
al, "A Processor In Memory Chip for Massively Parallel Embedded
Applications," IEEE Journal of Solid State Circuits, Oct. 1996, pp.
1556-1559.
- Kogge, Peter M.,
"Function Based Computing and Parallelism: A Review," Parallel
Computing, Vol. 2, No. 3, Nov. 1985,pp. 243-253.
- Kogge, Peter M., "An
Architectural Trail to Threaded Code Systems," IEEE Computer, March,
1982, pp. 22-32.
- Kogge, Peter M.,
"Parallel Algorithms for the Efficient Solution of Recurrence
Problems," IBM Journal of R&D, Vol. 18, N. 2, March 1974,
pp.138-148.
- Kogge, Peter M. and H.S.
Stone, "A Parallel Algorithm for the Efficient Solution of a General
Class of Recurrence Equations," IEEE Trans. on Computers, vol. 22,
no. 8, Aug., 1973, pp. 786–793.
Refereed Conferences
- Timothy J. Dysart and Peter
M. Kogge. "Probabilistic Analysis of a Molecular Quantum-Dot Cellular
Automata Adder." 22nd IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems (DFT
'07). Rome, Italy.
September 26-28, 2007.
- Srinivas Sridharan, Arun
Rodrigues, and Peter Kogge, “Evaluating synchronization techniques
for light-weight multithreaded/multicore
architectures,”: 19th ACM symposium on Parallel algorithms and architectures
(SPAA '07), June 9-11, 2007,
San Diego, 2007
- S.E. Frost-Murphy, E.P.
DeBenedictis, P.M. Kogge, “General Floorplan
for Reversible Quantum-dot Cellular Automata,” ACM Int. Conf. on
Computing Frontiers, May 7-9, 2007.
- James Kramer, Matthias
Scheutz, Jay Brockman, and Peter Kogge, “Facing up to the Inevitable:
Intelligent Error Recovery in Massively Parallel Processing in Memory
Architectures,” 2006 Int. Conf. on Parallel and Distributed
Processing Techniques and Applications (PDPTA'06), June 26-29, 2006, Las
Vegas
- Richard Murphy, A. Rodrigues,
P. Kogge, and K. Underwood, “The Implications of Working Set
Analysis on Supercomputing Memory Hierarchy Design," 2005 Int. Conf.
on Supercomputing (ICS), Cambridge, MA,
June 20-22, 2005.
- Koudriavtsev, Alexei and
Peter M. Kogge, "Generation of Permutations for SIMD
Processors," ACM Conf. on Languages, Compilers, and Tools for
Embedded Systems (LCTES'05), June
15-17, 2005, Chicago, IL.
- Arun Rodrigues, Richard
Murphy, Peter Kogge, Keith Underwood, "Characterizing a New Class of
Threads in Scientific Applications for High End Supercomputers," 8th
annual ACM Conf. on Supercomputing, June 24-July 1, 2004, Saint Malo, France.
- Sarah E. Frost, Timothy
Journal Dysart, Peter M. Kogge, Craig S. Lent, "Carbon Nanotubes for
Quantum-dot Cellular Automata Clocking," 4th IEEE Nano Conf., Munich,
Germany, Aug. 17-19, 2004.
- Antonelli,
Dominic A., Timothy Journal Dysart, Danny Z. Chen, Xiabobo
S. Hu, Andrew B. Kahng, Peter M. Kogge, Richard
C. Murphy, and Michael T. Niemier, "Quantum Dot Cellular Automata
(QCA) Circuit Partitioning: Problem Modeling and Solutions," 41st
Design Automation Conf. (DAC), June 7-11, 2004, San Diago,
CA.
- Michael T. Niemier and Peter
M. Kogge, "The 4-Diamond Circuit-A Minimally Complex Nanoscale
Computational Building Block in QCA," IEEE Symp.
on VLSI (ISVLSI), Lafayette, LA,
Feb. 2004, pp. 3-10.
- Timothy Journal Dysart, Branden Journal Moore, Lambert Schaelicke, and Peter
M. Kogge, "Cache Implications of Aggressively Pipelined High
Performance Microprocessors," IEEE Int. Symp.
on Performance Analysis of Systems and Software (ISPASS), Austin,
TX, March 10-12, 2004.
- Arun Rodrigues, Richard
Murphy, Peter Kogge, Jay Brockman, Ron Brightwell,
Keith Underwood, "Implications of a PIM Architectural Model for
MPI," Clusters, Hong Kong, Dec. 2003.
- Timothy Journal Dysart and
Peter M. Kogge, "Strategy and Prototype Tool for Doing Fault Modeling
in a Nano-Technology," IEEE Nano Conf., San
Francisco, CA, Aug. 12-14, 2003.
- Peter M. Kogge, Jeffrey Nankung, Nazeeh Aranki, N. Benny Toomarian,
Kanad Ghose, "Characterization of Future Deep Space Computing
Loads," Space Mission Challenges for Information Technology (SMC-IT),
Pasadena, CA, July, 2003.
- Sarah Frost, Arun Rodrigues,
Charles Giefer, and Peter M. Kogge,
"Bouncing Threads: Merging a new execution model into a
nanotechnology memory," IEEE Annual Symp.
on VLSI, Feb. 20-21, 2003.
- Gary E. Bernstein, Jay B.
Brockman, Gregory L. Snider, Peter M. Kogge, and Barbara E. Walvoord, "From Bits to Chips: A
Multidisciplinary Curriculum for Microelectronic System Design
Education," Midwest Conf. of ASEE, April 12, 2002.
- Michael T. Niemier and Peter
M. Kogge, "Exploring
and Exploiting Wire-Level Pipelining in Emerging Technologies",
Int. Symp.of Computer Architecture (ISCA), Sweden,
July 2001. pp. 166-177
- Gurhan
Kucuk, Kanad Ghose, Dmitry
Ponomarev, Peter Kogge, "Energy Efficient
Instruction Dispatch Buffer Design for Superscalar Instruction Dispatch
Buffer Design for Superscalar Processors," Proc. ACM Int. Symp. on Low Power Electronics and Design (ISLPED),
2001, pp. 237-243.
- Zyuban,
Victor and Peter M. Kogge, "Optimization of High-Performance
Super-Scalar Architectures for Energy-Delay Product," ACM/IEEE Int. Symp. on Low Power Electronics and Design, July 2000, Portofino, Italy
- Yerosheva, Lilia and Peter M.
Kogge, "Prototyping HTMT Execution Model Using Petri Nets,"
World MultiConf. on Systemics,
Cybernetics and Informatics, July 23-26, 2000, pp.318-323.
- Niemier, M.T., Kontz, M.Journal, and Kogge,
P.M. "A Design of and Design Tools for a Novel Quantum Dot Based
Microprocessor," 37th Design Automation Conf. (DAC), ACM Press, Los
Angeles, CA, June 2000,
pp. 227-232.
- Hall, Mary, Peter Kogge, Jeff
Koller, Pedro Diniz,
Jacqueline Chame, Jeff Draper, Jeff LaCoss, John Granacki, Apoorv Srivastava, William Athas, Jay Brockman, Vincent Freeh,
Joonseok Park, Jaewook
Shin. "Mapping Irregular Applications to DIVA, A PIM-based
Data-Intensive Architecture," Supercomputing, Nov. 1999
- Niemier, Michael and Peter M.
Kogge, "Logic in Wire: Using Quantum Dots to Implement a
Microprocessor," Proc. of the Int. Conf. on Electronics, Circuits and
Systems (ICECS), Larnaca,
Cyprus, Sept. 1999
- Brockman, Jay B., Peter, M.
Kogge, Vincent Freeh, and Thomas Sterling,
"Microservers: A New Memory Semantics for
Massively Parallel Computing," Int. Conf. on Supercomputing, Rhodes,
Greece, June 20-25, 1999, pp. 454-463.
- Niemier, Michael and Peter M.
Kogge, "Designing Complex Logic Systems with QCA Devices," Great
Lakes Symp. on VLSI, Ann Arbor MI, March 2-4,
1999. pp. 122-125.
- Zyuban,
Victor and Peter M. Kogge, "The Energy Complexity of Register
Files," Int. Symp. on Low-Power Electronics
and Design, Monterey, CA, Aug. 10-13, 1998, pp. 305-310.
- Sterling,
Thomas and Peter M. Kogge, "An Advanced PIM Architecture for Spaceborne Computing," 1998 IEEE Aerospace Conf.
Proc., March 21-28, 1998.
- Tian,
Yi, Edwin H.M Sha, Chantana
Chantrapornchai, and Peter M. Kogge,
"Optimizing Data Scheduling on Processor-In-Memory Arrays," Int.
Parallel Processing Symp.(IPPS),
Orlando, FL,
March 30 - April 3, 1998.
- Nanayanaswamy,
Lakshmi and Peter M. Kogge, "Combinators-In-Memory: An Unconventional Approach to
Avoiding the Memory Wall," 1st Int. Conf. on Unconventional Models of
Computation, Auckland, NZ, Jan. 5-8, 1998.
- Tian,
Yi, Edwin Sha, Chantana
Chantrapornchai, and Peter M. Kogge,
"Efficient Data Placement for Processor-In-Memory Array
Processors," 9th Int. Conf. on Parallel and Distributed Computing and
Systems, Washington D.C.,
Oct. 13-16, 1997.
- Surma,
David, Edwin Hsing-Mean Sha,
and Peter M. Kogge, "SCORE: An Efficient Technoque
to Reduce Congestion in Parallel Systems," 10th Int. Conf. on
Parallel and Distributed Computing Systems, New Orleans, LA, Oct. 1-3,
1997.
- Sheliga,
M., E. Sha, Peter M. Kogge, "Compression
Using the EXECUBE Processor Array," IEEE National Aerospace and
Electronics Conf., Dayton, OH,
July 14-18, 1997.
- Kogge, Peter M., S. C. Bass,
Jay B. Brockman, D. Z. Chen, E, H. Sha,
"Pursuing a Petaflop: Point designs for
100TF Computers Using PIM Technologies," 6th Symp.
on Frontiers of Massively Parallel Computation, Annapolis, MD, Oct. 25-31,
1996.
- Ghose, Kanad, Kiran R. Desai, and Peter M. Kogge, "Using Method
Lookup Caches and Register Windowing to Speed Up Dynamically-Bound
Object-Oriented Applications," Proc. 22nd Euromicro,
pp.441-448, Sept. 1996
- Brockman, Jay, S. Batill,
Journal Renaud, Journal Kantor, D. Kirkner,
Peter M. Kogge, R. Stevenson, "Development of a Multidisciplinary
Engineering Design Laboratory at the University
of Notre Dame," Proc.
ASEE Annual Conf., Wash.
D.C., June 23-26, 1996.
- Kogge, Peter M., T. Giambra, H. Sasnowitz,
"RTAIS: An Embedded Parallel Processor for Real-time Decision
Aiding," 1995 NAECON, Dayton, OH,
March, 1995
- Kogge, Peter M., T. Sunaga,
E. Retter, et al, "Combined DRAM and Logic
Chip for Massively Parallel Applications," 16th IEEE Conf. on
Advanced Research in VLSI, Raleigh, NC, IEEE Computer Society Press #
PR07047 , March 1995, pp. 4-16
- Kogge, Peter M., "The EXECUBE
Approach to Massively Parallel Processing," 1994 Int. Conf. on
Parallel Processing, Chicago, IL, pp. 77-84, August, 1994.
- Kogge, Peter M.,
"Declarative Computing: A Technology Driver," Architectektur von Rechensystemem,
Springer Verlag, pp. 1-17, 1992.
- Kogge, Peter M., Journal Mastranadi and T. Giambra,
"The Real Time Artificial Intelligence System," NAECON, Dayton,
OH, May 1992
- Kogge, Peter M., John Oldfield, et al, "VLSI and Rules Based
Systems," Chap. 4.1 of VLSI for Artificial Intelligence, ed. J. G.
Delgado Frias and W. R. Moore, Kluwer Academic Press, 1990
- Kogge, Peter M.,
"Algorithm Development for Pipelined Processors," Int. Conf. on
Parallel Processing, Bellaire, MI,
Aug. 1977
- Kogge, Peter M., "The
Microprogramming of Pipelined Processors," 4th Int. Symp. on Computer Architecture, Silver
Spring, MD, March 1977
- Kogge, Peter M.,
"Parallel Algorithms for the Efficient Solution of Recurrence
Problems," (early version of IBM Journal paper), 7th Annual Princeton
Conf. on Info. Sciences and Systems, March 1973
- Kogge, Peter M.,
"Maximal Rate Pipelined Solutions to Recurrence Problems," 1st
Annual Symp. on Comp. Architecture, Gainesville,
FL, Dec. 1973
Refereed Workshops and Workshops with Proceedings
- Peter M. Kogge, “The
Shape of Things to Come: Future Potential of “Heavy Node”
Multi-Core HPC Architectures” Int. Workshop on Innovative
Architectures (IWIA), Hilo, HI,
Jan. 2008.
- Timothy J. Dysart and Peter
M. Kogge. "Probabilistic Analysis of a Quantum-Dot Cellular Automata
Multiplier Implemented in Different Technologies." 4th Non-Silicon
Computing Workshop in conjunction with the 34th Int. Symp.
on Computer Architecture and FCRC 2007. San
Diego, CA. June
9, 2007.
- Sheng
Li, Amit Kashyap,
Shannon Kuntz, Jay Brockman, Peter Kogge, Paul Springer, Gary Block, “A Heterogeneous
Lightweight Multithreaded Architecture,” Workshop on Multithreaded
Architectures and Applications (MTAAP’07) associated with 21st IEEE Int. Parallel
& Distributed Processing Symp. (IPDPS), March 26-30, 2007, Long
Beach, CA
- Peter M. Kogge, “Some
Initial Explorations into the Hierarchical Multi-Core Chip Design Space
for HPC Systems” Int. Workshop on Innovative Architectures (IWIA), Maui,
HI, Jan. 2007, pp. 3-10.
- Sridharan, Srinivas, Brett
Keck, Richard Murphy, Surendar Chandra, and Peter
Kogge, “Thread Migration to Improve Synchronization
Performance,” in the Proc. of the 2006 Workshop on Operating Systems
Interference in High Performance Applications (OSIHPA 2006), in
conjunction with PACT 2006, Seattle, WA, September 17, 2006.
- Dysart, Timothy and Peter M.
Kogge, "An Analysis of Missing Cell Defects in Quantum dot Cellular
Automata," 1st IEEE Int. Workshop on Design and Test of Defect
Tolerant Nanoscale Architectures, (NANOARCH'05) in conjunction with IEEE
VLSI Test Symp., May 1-2, 2005, Palm Springs,
CA.
- Peter M. Kogge, “An
Exploration of the Technology Space for Multi-Core Memory/Logic Chips for
Highly Scalable Parallel Systems,” Int. Workshop on Innovative
Architectures (IWIA) 05, Turtle Bay, HI,
Jan. 18-19, 2005.
- Brockman, Jay, S. Thoziyoor,
S. Kuntz, P. Kogge. “A Low Cost, Multithreaded Processing-in-Memory
System.” 3rd Workshop on Memory Performance Issues, held in
conjunction with Int. Symp. on Computer
Architecture (ISCA)-2004, Munich,
Jun. 20, 2004.
- Peter M. Kogge, “Of
Piglets and Threadlets: Architectures for
Self-Contained, Mobile, Memory Programming,” Int. Workshop on
Innovative Architectures (IWIA)’04, Maui
Supercomputer Center, HI, Jan. 12-13, 2004.
- Peter M. Kogge, Jeffrey Nankung, Nazeeh Aranki, N. Benny Toomarian,
Kanad Ghose, "A Comparative Analysis of Power and Energy Management
Techniques in Real Embedded Applications," IEEE Int. Workshop on
Innovative Architectures (IWIA'03), Kauai, HI, Jan. 2003.
- Richard C. Murphy and Peter
M. Kogge, "Trading Bandwidth for Latency: Managing Continuations Through a Carpet Bag Cache," IEEE Int. Workshop on
Innovative Architectures (IWIA'02), Kona HI,
Jan. 2002.
- Murphy, Richard, and Peter M.
Kogge, "The Characterization of Data Intensive Memory Workloads on
Distributed PIM Systems," Intelligent Memory Systems Workshop,
ASPLOS-IX 2000, Boston, MA, Nov. 12, 2000.
- Kudriavtsev,
Alexei, and Peter M. Kogge, "SMT Possibilities for Decoupled
Architectures," Memory access decoupling for superscalar and multiple
issue Architectures (MEDEA) Workshop, Int. Conf. on Parallel Architectures
and Compilation Techniques, Philadelphia, PA,
Oct. 19, 2000.
- Yerosheva (Suslov), Lilia and Peter M. Kogge, "Prototyping
Execution Models for HTMT Petaflops Machine in Java," 3rd Workshop on
Communications, Architecture, and Applications for Network-based Parallel
Computing, in conjunction with 5th Int. Symp. on
High Performance Computer Architecture, Orlando, FL, Jan. 9-13, 1999.
- Kogge, Peter M., Jay B.
Brockman, Vincent Freeh, "PIM Architectures
to Support Petaflops Level Computation in the HTMT Machine," IEEE
Int. Workshop on Innovative Architectures (IWIA'02), Maui
HI, Jan. 2002, pp. 35-44.
- Kogge, Peter M., Jay B.
Brockman, Vincent Freeh,
"Processing-In-Memory Based Systems: Performance Evaluation
Considerations," Workshop on Performance Analysis and its Impact on
Design - PAID'98, held in conjunction with Int. Symp.
on Computer Architecture, Barcelona, Spain, June 27-28, 1998.
- Zyuban,
Victor and Peter M. Kogge, "Split Register File Architecture for
Inherently Lower Power Architectures," Workshop on Power-Driven
Microarchitecture, held in conjunction with Int. Symp.
on Computer Architecture (ISCA), Barcelona, Spain, June 27-28, 1998.
- Zawodny,
Jason T., Jay B. Brockman, Peter M. Kogge, Eric Johnson, "Cache-In-Memory:
A Lower Power Alternative," Workshop on Power-Driven
Microarchitecture, held in conjunction with Int. Symp.
on Computer Architecture (ISCA), Barcelona, Spain, June 27-28, 1998.
- Daescu,
Ovidiu, Peter M. Kogge, and Danny Chen,
"Parallel Content-Based Image Analysis on PIM Processors," IEEE
Workshop on Content-Based Access to Image and Video Databases, June 21,
1998.