Molecular Architecture Workshop
An NSF-Sponsored Workshop at the University of Notre Dame
Nov. 12, 13, 2001

As you may know, NSF has launched a major 5 year initiative on Nanoscale science and engineering (NSE) - . Its goals include fundamental understanding of nanoscale phenomena, synthesis and processing of nanodevices, and design of novel materials. Through support for research on computational methods and multiscale simulation techniques, the CISE directorate plays an important role in the physics of such phenomena.

However, there is another aspect of molecular manufacturing where CISE and its associated community have talents that are uniquely applicable to NSE. This is the area of architecture and design. To analyze and synthesize complex systems, the computer design tradition is to impose upon the basic technologies the concept of architecture, and to use multiple layers of abstraction, often with different mathematical models, languages and formalisms, to represent component interactions at different layers. Over the last 30 years, as new generations of silicon-based technology have appeared, new system bottlenecks have surfaced (memory latency, inter-instruction dependencies, clock distribution, power, off-chip bandwidth, etc.). In response, the computer architecture community has developed new architectural concepts and execution models (RISC, memory consistency models, vectors, VLIW, multi-threading, shared and distributed memory models), new subsystems and microarchitectural techniques (caches, pipelining, multi-way issue, branch prediction), new circuit design techniques (dynamic logic, clock distribution and gating, voltage scaling), new floorplanning and layout concepts (custom, standard cell, gate array, and field reprogrammable designs), and new design abstractions (high level design languages, synthesis, systems on a chip). This has happened largely because the architecture community has been working hand in hand with the device, circuits, and CAD communities.

In some sense this process has worked too well for silicon, with areas such as computer architecture now widely believed to have reached the level of a matured technology, where only incremental improvements are possible, and the big conceptual breakthroughs are largely in the past. In contrast, in the last few years a variety of new technologies have emerged which have the potential for designing artifacts of all sorts, including computers, at the molecular level. In terms of relevance, nanometer scale devices have the potential to extend Moores Law literally orders of magnitude beyond the edge of the conventional silicon roadmap of 35 nm in 2014. The problem, however, is that the community working in such technologies has been largely limited to the physical scientists. While this is sufficient to permit demonstrations of device-level feasibility, and perhaps simple circuits and subsystems, what is lacking is an appreciation for the techniques needed to scale the applicability of such technologies up to the regions where they can be regarded as serious contenders to silicon. Experience in understanding system-level constraints and how to modify low level circuit and device level parameters to overcome them is largely lacking. This is true not just for using such technologies for molecular level computing systems, but for any molecular level system of sufficient complexity where the lessons of hierarchical design and design abstractions will become important.

Given this, the timing is right for assembling a cross-disciplinary group to stimulate such discussions and prepare for near term new research opportunities. Besides the NSE initiative (with first deadlines expected in early December). NSF, for example, is also looking for creative work in its CSA (deadline: 12/5/01) and ITR (deadlines 11/12/01 and 2/6/02) programs.