Tuesday:

Final Examination: 4:15 to 6:15 PM in 356 Fitzpatrick

Design Validation

Design for Test

Project Reviews

Meet in EE Conference Room 12pm-3pm (pizza provided).

Weste and Harris: Chapter 9, Testing and Verification

• Homework 11 Due Wed. Dec. 9 (last class day)
  • Power: 4.27 but assume 90 nm process with 75 pF/mm2, a 100 mm2 chip, 900MHz, and a Vdd 0f 0.6V, 4.28
  • Wire: 4.30
  • Scaling: 4.36
  • Understand the solution to 4.37
• Do the odd problems in Chapter 9 on your own. The answers are available at the W&H CMOS VLSI Website

Power Class notes (revised 12/1)

Interconnect - a.k.a. Wire (Class Notes (revised 12/1))

Meet in Classroom

Scaling (Class Notes)

Weste and Harris:

Power: 4.4

Wire: 4.5 and 4.6

Scaling: 4.9

• Homework 11 Due Wed. Dec. 9 (last class day)
  • Power: 4.27 but assume 90 nm process with 75 pF/mm2, a 100 mm2 chip, 900MHz, and a Vdd 0f 0.6V, 4.28
  • Wire: 4.30
  • Scaling: 4.36
  • Understand the solution to 4.37
• Homework 10 due Friday Dec.4. Weste and Harris 11.1 and 11.2. (These problems should only take a few minutes but read Problem 11.1 carefully.)

• By Monday Nov. 30 send an email status on project progress to Profs. Kogge & Nahas containing: Title, Goal, Accomplishments to Date, Major Work Left to Do, Potential Impediments.

Meet in Engineering Learning Center for class

Labatory 7: Logic Synthesis and Place-and-Route (Handout)

Thanksgiving Holiday

Thanksgiving Holiday

Brunvald Sections 9.2 to 9.5 and Chapter 11

Homework 10 due Friday Dec.4. Weste and Harris 11.1 and 11.2. (These problems should only take a few minutes but read Problem 11.1 carefully.)

Work on Project.

By Monday Nov. 30 send an email status on project progress to Profs. Kogge & Nahas

• Title:
• Goal:
• Accomplishments to Date:
• Major Work Left to Do:
• Potential Impediments:

Review of Exam 2, Question 2

Review of Analog Simulation Lab

Analog Part 2 continued (Version 4 of Part 2)

Analog Part 3 - Digitial to Analog Converters (Class Notes)

Meet in Classroom

Memories (Class Notes)

Weste and Harris:

Analog Design: 12.6

Memory: 11.1 to 11.2.3, 11.3.0, 11.4.0 to 11.4.1.

Brunvald Ch. 7

Reminder: Hand in amplifier Gain and Gain Phase plots from the 11/13/09 Lab.

Homework 8 due Friday Nov. 20. Weste and Harris 12.7, 12.8, 12.15

Homework 9 due Frida, Nov. 20. Weste and Harris 12.12, 12.13 (Greatly Expanded Hints)

Instead of Weste and Harris 12.9 and 12.10 use this problem. It is a similar problem but uses the amplifiers from the lab to save your creation of a new schematic.

Homework 10 due Friday Dec.4. Weste and Harris 11.1 and 11.2. (These problems should only take a few minutes but read Problem 11.1 carefully.)

Analog Part 3 continued (Version 3 of Part 2)

Exam Review

Exam Topics

Updated Multi Stage Summary

Optimal Number of Stages

Exam II

Labatory 6: Analog Simulation - Operation Amplifier

Weste and Harris, 12.6

Brunvald Ch. 7

Homework 8 due Friday Nov. 13. Weste and Harris 12.7, 12.8, 12.15

Homework 9 due Friday Nov, 20. Weste and Harris 12.9, 12.10, 12.12, 12.13

Logic Effort - Continued (MultiStage Circuits Summary)

Analog Design - Part 1: Mirrors and Matching

Analog Design - Part 1 continued and Part 2:Amplifiers and Small Signal Model (Version 2)

Analog Design - Part 2 continued. (New version of Part 2.)

Weste and Harris, Section 12.6

Drennan and McAndrew papers on Transistor Matching (Available on the Links page.

Homework 7 due Friday Nov. 6

Homework 8 due Friday Nov. 13. Weste and Harris 12.7, 12.8, 12.15

Homework 9 due Friday Nov, 20. Weste and Harris 12.9, 12.10, 12.12, 12.13

Logical Effort Part 1

(Logical Effort Part 2)

Sample Logical Effort Problem Solving

Weste and Harris, Section 4.1 - 4.3

Discussion of DC Response of Gates

Dynamic Logic Families(Handouts)

Meet in Engineering Learning Center for class

Labatory 5: Design Rule Checking (DRC) and Layout versus Schematic (LVS)

Weste and Harris, Section 2.5, 2.4.2, 6.2

Hint for Homework: If you want to see more than the top level of signals, i.e. the signals in the testbench, in SimVision:

• In the NC-Verilog window, select Setup->Record Signals...
• In the Record Signals window, increase the number of levels in the box at the bottom. (Note, the All button does not seem to work as expected.)

Initial Project Descriptions due Friday Oct. 16 (See Projects Page)

Exam 1(Prep Guide)

Discussion of Project Constraints

Meet in Engineering Learning Center for class

Labatory 4: Using Verilog under Cadence(Handouts)

Brunvand Chap. 4

Also see Project Pages for sample code files

Complete Verilog Review (Handouts)

Start MIPS complete Verilog design example (MIPS Overview)

Finish MIPS complete Verilog design example (Handouts)

(Behavioral MIPS code)

(Structural MIPS code)

Exam topics review

Final project discussion

Meet in regular class - 326

Exam review (Topics)

W&H Chap. 1.7 and Appendix B.7

Brunvand Chap. 4

Additional Material on Verilog: Ciletti, "Starter's Guide to Verilog 2001"

Homework 5, due Friday Oct. 2

Intro to the CMOS Transistor - Part C(Handouts)

Introduction to Verilog (Handouts)

Meet in Engineering Learning Center for class

Labatory 3 (again): Redo of Virtuoso Lab (Lab Notes)

W&H: Appendix A (Verilog)

Brunvand Chap. 4

Additional Material on Verilog: Ciletti, "Starter's Guide to Verilog 2001"

Homework 4, due Friday Sept 25

Homework 5, due Friday Oct. 2

Intro to the CMOS Transistor - Part A(Handouts)

Meet in Engineering Learning Center for class

Labatory 3: Custom Layout with Virtuoso ('08 Video)

Homework 3, due Friday Sept 18

Homework 4, due Friday Sept 25

Intro to the CMOS Process(Handouts)

Meet in Engineering Learning Center for class

Labatory 2: Schematic Capture and Transient Simulation using Cadence Composer and Spectre ('08 Video)

Homework 2, due Friday Sept 11

Homework 3, due Friday Sept 18

Basic CMOS Gates(Handout)

Meet in Engineering Learning Center for class

Labatory 1: Initializing Cadence in the ND Environment (Handout)

Tutorial/Demo: Schematic Design and Simulation in Cadence ('08 Videos)

Homework 1, due Friday Sept 4

Homework 1, due Friday Sept 4

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