CSE 462 VLSI Design, Homework 1
Due Monday September 6, 2004
- Do the Mach-TA tutorial.
For your "solution", submit your corrected test vector file for
the NAND gate and state what messages MTA produced when it found a
comparison error and when it found no errors with the vectors.
- Draw a schematic for a CMOS AND gate using 2 n-type devices in the pull-up
network and 2 p-type devices in the pull-down network. Using MTA,
simulate the circuit with both inputs high and then with one input high and
one input low. What is the output voltage for a logical 1 (high) and
logical 0 (low). Explain why you get these voltages.
- Develop an MTA input file for the carry-out circuit of a mirror adder and
write a test vector file that exercises all possible combinations of the
inputs to the circuit. Notice that the mirror adder is not a
complementary circuit, and that the pull-up network is a "mirror"
of the pull-down network. Redesign the circuit so that the pull-up is
the complement of the pull-down. Test your design using MTA with the
same test vector file as was used for the mirror adder. Turn in the
schematic for the redesigned circuit and the test vector file.
- Using the water model analogy, briefly explain the effect of fan-out (how
many gates the circuit drives at its output) on propagation delay for a CMOS
circuit.
- (Revised Friday, Sept. 3) A computer architect has proposed that the performance of a certain
microprocessor could be improved by 50% by doubling the size of the
cache. If the cache is half of the area of the die, what would be the
die yield of both designs. Assume that the defect density is the same,
1 per square cm, that the area of the original design is 2 square cm, that the value for alpha is 4.
How many die of both the original design and of the new design could fit
onto a wafer 20 cm in diameter? What would be the number of good die
per wafer from both designs.