Schematic Capture and HSPICE Netlist Extraction

(modified and augmented for ND CSE 462 from Dave Zar's ADK/SDL Tutorial)

In this tutorial, you'll learn how to use Mentor's schematic capture program, Design Architect, to draw a NAND gate schematic. You'll then use another tool, DA Netlister, to convert the Mentor schematic to an HSPICE file for simulation. You will use N-FETS and P-FETS from the Mentor Graphics ASIC Design Kit (ADK) library, as these components have the necessary properties assigned that support automatic layout of transistors (Schematic-Driven Layout, or SDL). After placing these FETS, you can wire them together and add ports and net names as you would any other design. You can even create hierarchical designs and then drive your layout from that.

Mentor Graphics Design Files and Directories

Before you do anything, the first thing that you should know about Mentor Graphics is that it is extremely particular with regard to the naming and location of files within the Unix directory system. Mentor tools provide good support for hierarchical designs, but they have devised a system that is built on top of the directory systems, not one that maps to it exactly. A single Mentor component typically takes multiple files to represent it, where some of these files contain references to other file locations.

Never attempt to move a Mentor design component using Unix commands, always use the design management commands provided within the Mentor tools. Failure to do so could result in losing design data.

When you save a design component in Mentor, a directory and several files are typically created to represent that component. It is highly inadvisable to place anything else in these component directories. To make matters worse, it is possible to accidently convert a regular directory into something that Mentor thinks is design component.

Be cautious and conservative when setting up a directory structure for Mentor designs. Be sure to check where you are saving something before you hit the "OK" button.

We strongly recommend that you use the following directory structure for your VLSI design projects. First, each project should have its own unique top-level directory (such as da_tut for this project). Within the project directory, create the following subdirectories:

parts: contains components created with Design Architect (and design viewpoints, which we won't worry about yet) and nothing else;
hspice: contains hspice input, output, and device model files;
physical: contains layouts created with IC station, and nothing else.

Create a Schematic and Symbol for a NAND Gate

At first, you need to run a short shell script before running Design Architect. Either execute from a command line or enter in your .cshrc file the following:

source /usr/local/src/idea/.mentor_d1

Create a directory called da_tut in your vlsi directory. Create the subdirectories in it as described above. We won't use physical, but there's no harm in getting used to creating it.

Setup yourSet the Mentor working directory to this directory by typing setenv MGC_WD parts

parts

adk_da&

Once DA is running, you can follow the steps outlined below to capture a 2-input NAND gate and a 2-input NOR gate.

Open a new sheet and call it nand2. (Note: if you're not sure what your current working directory is, it's always safest in Mentor to type in the full AFS path name, e.g. /afs/nd.edu/userxx/..../nand2, for the component). The following few instructions will step you through drawing the schematic for a 2-input NAND gate as shown in Figure 1.

Figure 1: 2-Input NAND Gate

Use the Libraries pull-down menu to select ADK Libraries which will show the ADK Libraries palette menu.

The top six entries in this palette will give you a list of standard cells that you can use from the supplied library. The Pads library will let you place schematic instances of the pads into your design. The last item, SDL Parts, will give you another palette menu with the parts you will use to build your custom design.

Click on SDL Parts to show the SDL Parts palette menu.

Now place two instances of the n-fet-4 (four-terminal n-fet) as shown in Figure 1. Some useful editing functions that you may need are

Left-click or drag over objects to select them
F2 to deselect
Right-click on a selected object to get popup menu with Move, Copy, Undo, Flip, others. (note operation applies to all selected objects)
Delete key to delete
ESC to get out of current operation

Using the same procedure, get and place two p-fet-4 instances.

Now place the VDD and VSS symbols from this same directory.

Get and place the portin and portout symbols from the SDL Parts menu. These are GENLIB parts and they are not specific to SDL. Hence, you can get them from anywhere. They are on the SDL palette for your convenience.

Wire up the components as shown in Figure 1. To do this follow the steps below

Right-click on the palette (currently contains ADK_Library) and select Display Schematic Palette
Left-click Add Wire. Draw the wires connecting the mosfets--left-click to start a wire or change direction, double-left-click to end a wire.
When done, press the ESC key to exit the Add Wire function and F2 to deselect the wires you just drew.

Now we should change the widths on the transistors, as well. We want to build a higher drive gate, so we need to make the transistors wider. Both p-fets should be 24 lambda wide and the n-fets should be 20 lambda wide when you're done. Don't change the length or any other properties on the fets. To change the width, place the cursor somewhere on the "W=5" text and type <shift>F7. In the popup window, enter the new value and click OK.

Change the input and output port names to A, B, OUT, using <shift>F7 as before.

You can now check and save the sheet. If you have any errors, be sure to fix them before going on.

to check, use main menu Check > Schematic (you'll probably get one error regarding the "interface" of the cell--ignore it, it will go away after you save the cell.
to save, use File > Save Sheet

Use the Miscellaneous->Generate Symbol menu item to automatically generate a symbol for you. Do not change any of the options in the dialog box and click on the OK button to generate your symbol.

Your symbol will be a simple rectangle with three pins. This is fine although you could modify the body of the symbol to look like a typical NAND gate graphic. We will, however, place the name of the gate on the box to help us remember it in the future. To do this, use the Edit->Add Graphics->Text menu and use the name NAND2 as the text. Place this text in the symbol.

Now you can check and save the symbol. You can ignore the warnings about the properties not being on the interface. If you have any other errors, however, you need to fix them before moving on.

Close the symbol window.

Create a Symbol and Schematic for an Inverter

In the same manner as above, open a new sheet for an inverter (called "inverter") and create a schematic and symbol for an inverter, as illustrated in Figure 2.

Fig. 2 Inverter Schematic and Symbol

Create an AND Gate

Next, we'll wire up the NAND gate and the inverter to create an AND gate. Open a new sheet called "and".
Click on Choose Symbol in the palette and select "nand" and place it in the schematic. Repeat for the inverter. Wire them together as shown in Figure 3. Check and save the schematic as before.

Fig. 3 AND gate Schematic

Extract an HSPICE Netlist

In the final step, we'll extract a netlist of the AND gate for HSPICE simulation. Before extracting the netlist, we need to create a Mentor design viewpoint of the AND gate. A script called sdl_prep has been created to perform this task. (SDL stands for "schematic-driven layout"--you'll learn more about this in a later tutorial). To run this script, from a Unix window, enter your parts directory and type

sdl_prep and

This will create several design viewpoints for later usage

The final step is to create a flattened HSPICE netlist. To do so, run the script flatnet

flatnet and/sdl and.spc

This will produce the netlist file and.spc, extracted from the sdl viewpoint of the and component. Look at the contents of the HSPICE output file. It should contain 6 transistors, connected as the AND gate.

Move the extracted HSPICE file into your hspice directory

mv and.spc ../hspice/

You're done. Print out the and.spc file and turn it in.