CSE 40547/60547:   Computing at the Nanoscale

Bonus Project:  Design for Manufacturability / Reliability of MRAM
Out:  11/30/07

In:  12/14/07

 

Much of the work that we have discussed in class has focused on the performance of single or a handful of devices.  Ultimately, if an emerging technology is to have impact and enter the marketplace, large-scale manufacturing and reliability issues must be addressed.  This paper talks about such efforts performed by researchers from Freescale concerning an implementation of MRAM.  Read ÒDemonstrated Reliability of 4-Mb MRAMÓ by Nahas, et. al. and answer the following questions. If you complete this assignment – and your score is better than your score for either HW1, 2, 3, 5, or 6 – you can replace that score with this score.

 

Question 1

What type of MRAM are the authors of the paper testing?  Briefly explain.

 

Question 2

Explain how (both physically and logically), time dependent dielectric breakdown can lead to less reliable MRAM devices.  Note that a good answer should also consider the frequency of MRAM bit ÒstressesÓ.

 

Question 3

Explain how (both physically and logically), time dependent resistance drift can lead to less reliable MRAM devices.

 

Question 4

The authors indicate that time dependent resistance drift, should not preclude an MRAM array from being reliable for > 10 years.  Obviously, a part was not continuously stressed/tested for 10 years.  How can they make this claim?  What experiments/testing were done to support this claim?

 

Question 5

The yoked copper wires (that make up word/bit lines) were also stressed.  Explain what mechanism would most likely cause such a wire to ÒfailÓ.