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Welcome to CSE 40462, VLSI Design, taught by Profs. Peter Kogge and Joseph Nahas in the Department of Computer Science and Engineering at the University of Notre Dame, and based on the same course as taught in prior years by Prof. Jay B. Brockman.

Note that the Exams are scheduled for Monday Oct. 5 and Wednesday Nov. 11, and the Final Exam is scheduled for Tuesday Dec. 15, 4:15 to 6:15pm

Link to Spring 2009 Logic Design course page for tutorials on Verilog, Xilinx, etc.

This week in VLSI Design

For prior weeks, see Calendar page.

Week 12: Nov 16 - Nov 20

Monday:

Review of Exam 2, Question 2

Review of Analog Simulation Lab

Analog Part 2 continued (Version 4 of Part 2)

Wednesday:

Analog Part 3 - Digitial to Analog Converters (Class Notes)

Friday:

Meet in Classroom

Memories (Class Notes)

Reading:

Weste and Harris:

Analog Design: 12.6

Memory: 11.1 to 11.2.3, 11.3.0, 11.4.0 to 11.4.1.

Brunvald Ch. 7

Homework:

Reminder: Hand in amplifier Gain and Gain Phase plots from the 11/13/09 Lab.

Homework 8 due Friday Nov. 20. Weste and Harris 12.7, 12.8, 12.15

Homework 9 due Frida, Nov. 20. Weste and Harris 12.12, 12.13 (Greatly Expanded Hints)

Instead of Weste and Harris 12.9 and 12.10 use this problem. It is a similar problem but uses the amplifiers from the lab to save your creation of a new schematic.

Homework 10 due Friday Dec.4. Weste and Harris 11.1 and 11.2. (These problems should only take a few minutes but read Problem 11.1 carefully.)

Week 13: Nov 23 - Nov 27

Monday:

Meet in Engineering Learning Center for class

Labatory 7: Logic Synthesis and Place-and-Route

Wednesday:

Thanksgiving Holiday

Friday:

Thanksgiving Holiday

Reading:

Brunvald Sections 9.2 to 9.5 and Chapter 11

Homework:

Homework 10 due Friday Dec.4. Weste and Harris 11.1 and 11.2. (These problems should only take a few minutes but read Problem 11.1 carefully.)

Work on Project.

Recent Web Site Changes

Following is a list of recent changes to the website:

  • (11/20/09: Hints for Homework 9 have been expanded and expanded again.
  • (11/19/09): Hints for Homework 9 added; 11/20 Class Notes added; Reading on Memories added; Homework 10 added.
  • (11/17/09): Added Weeks 12 and 13 information to Home page and Calendar; updated homework due 11/20/09.
  • (11/13/09): Lab Notes for 11/13 added; Homework 8 due date changed to 11/20; Extra Credit due 11/13
  • (11/9/09): Updated exam prep materials
  • (11/6/09): Updated notes for Analog Design - Part 2
  • (11/4/09): Links to Drennan and McAndrew papers added to Links page.
  • (11/4/09): Class Schedule updated; Homework 8 modified; Homework 9 due Nov. 20 added.
  • (11/4/09): Homework 8 added. Due Friday, Nov. 13.
  • (11/2/09): Next Exam on Wednesday, November 11
  • (11/2/09): Updated Week 10 in both Calendar and on Main Page; Lecture Notes Posted
  • (10/28/09): Significantly revised Lecture 7B posted; class on 10/30 will be in regular classroom; Exam#2 scheduled for 11/11
  • (10/14/09): Calendar on hompage updated to include Wed. lecture notes
  • (10/13/09): Calendar on Home Page updated; Monday's lecture notes added; Hint added for homework due Friday.
  • (10/9/09): Instructions for accessing Verilog from Cadence listed on "Projects" page along with some sample code.
  • (10/7/09): Cadence Documentation link added to and Brunvand Book link deleted from ND Only page.
  • (10/5/09): Links to 2008 project presentations added to Projects page.
  • (10/2/09): Review slides added to Friday
  • (10/2/09): Homework solutions for homeworks 01, 02, 03, 04, and 05 added to Assignments page.
  • (9/30/09): Posted: Topics for Exam #1
  • (9/29/09): Hints for running simulations and doing Homework 5 added to Home page.
  • (9/29/09): Administration page updated with Office Hours