Overview Administration Calendar Lecture Notes Assignments Links Change Log

This is a three credit course taught each Fall semester under four course listings to Electrical Engineering (EE) and Computer Engineering (CSE) and undergraduate (40462) and graduate (60462) students.

Instructor

Classroom:

Companion Web Site

The main text book, Weste and Harris 4th edition, has a strong companion web site, including ANSWERS TO ODD QUESTIONS.

Administration

See Administration page for information on grading, office hours, etc.

Announcements

None

This week in VLSI Design

Week 16: Dec. 11 - Dec. 13

Previous weeks calendars, including class, readings, and homework information, are on the Calendar page.

Recent Web Site Changes. See Change Log for complete list

• 12/11: Posted solution to HW 8 and a Summary
• 12/6: Class Meeting: 356A Fitz, Tuesday 12/11, 1-3pm. Send in topics for discussion via email. Last homework will be accepted until 5pm Friday. Solutions to HW7 and Exam2 posted on Assignments page.
• 12/4: Change of 12/6 lecture to Scaling. Added 1st Draft of Final Exam Topics
• 11/28: If anyone wants some extra credit, I'd suggest submitting a complete structural Simple 12 including all instructions and the ISNZ, with printout showing the working code for both the original and the multiply. Value of extra credit = 3 points, or about 1/5 of an exam.
• 11/28: modified the homework 7 slightly.
• 11/26: Week 14 posted.
• 11/20: Final Exam is 10:30-12:30 Wed Dec. 12.
• 11/20: Posted most graduate student presentations under Assignments.
• 11/20: Finished in class notes on Delay. For those of you who were gone, you want to be able to draw the capacitances in a logic gate circuit, and then be able to draw RC circuits for worst and best cases of rise and fall times, as discussed in Section 4.3.5. Note: error in book on page 152, Example 4.7 Fig. 4.15(b) is for "rising" edge not falling.
• 11/19: Updated to Week 13