Morph: Morphable Computer Architectures for Highly Energy-Aware Systems
"Adding an Energy Gear to High Performance Embedded Systems"

General Problem: Current embedded systems exhibit a mix of power sources and operational modes, which result in huge variations in compute needs. Today's design practice, however, designs for the high performance peak, and utilizes relatively simplistic "low power modes" for other times. Despite these modes, the resulting systems are still nowhere near as energy efficient as systems built from the ground up for minimal energy useage. The latter, however, do not have the computational potential needed for future embedded systems. The results are either systems with too high an energy consumption, or too low a performance capability.

Specific Problem: To achieve a revolutionary reduction in overall power consumption, computing systems must be constructed out of both inherently low-power structures and power-aware (or even better energy-aware) hardware and software subsystems. Today's most prevalent practices involve simple frequency scaling and modes where subsystems are merely powered on or off as needed. The energy expended per computational event (memory access or issuance of new instructions) is not, however, adjustable, even when lower than peak performance is acceptable. This is particularly true as we move towards memory intensive hierarchical systems (register files, caches, SRAM, DRAM, Flash, ..) where placement of data within the hierarchy has as much effect on energy expenditures as lowering the logic power. It will become even more true with embedded systems on a chip. Thus, to go significantly beyond the current state of the art requires architectures with a wide dynamic range in adjust-able performance/energy settings, and run-time software to dynamically manage these settings against real-time constraints. Further, this must be coupled with support for programmer or compiler specifiable "hints" as how to most efficiently utilize the available energy.

The Morph Solution: design an architecture which can dynamically match system performance capabilities to the current needs, and reap the energy savings from running in a more energy efficient mode.

Major Morph Goals: Consequently, the Morph project has two major goals: first, to develop architectures whose energy/performance characteristics can be shaped to meet available energy profiles, and second to develop tools and software which will configure the system and place and manage data within a system so that these energy saving techniques can be achieved. Overall, this should provide a rich suite of solution techniques which will be useable in a wide variety of implementations and for a wide variety of mission applications.

Specific Approaches: In particular, this project will utilize several innovative approaches to achieving this control:

• A morphable "multi-cluster" CPU organization where, besides frequency, the "width" of concurrent instruction issue ("w") is a parameter.
• Morphable memory hierarchies where memory segments with different or variable latency/energy characteristics, for both memory and cache, are present in the same system.
• Development of algorithms for "placing" data within such memory hierarchies in not just a "performance aware" but also an "energy aware" fashion, and then once the data is placed, to control how the memory structure is used for maximum energy efficiency.
• Inclusion in the "variable w" architecture of instructions which permit multiple data operands to be processed at once, thus amortizing the energy expended for instruction fetch and issue, and data fetch, over more operations.
• Inclusion in the variable w architecture of facilities for using unused clusters for additional program threads, which otherwise would cause energy-wasting context switches.
• Adaptive algorithms which can take mission energy/performance profiles and select settings for the morphable architecture to meet them.
• Prototype run-time extensions to track and enable the changing of these energy management configuration parameters, and APIs which allow program-specified hints to be considered.
• Adaptation of the run-time operations and data structures to themselves be energy aware.
• Implementation approaches to such systems which vary from approximations using currently available chip sets, through new variable w chip set designs, to system designs where the appropriate configuration for some w can be downloaded into reconfigurable logic as required.
• Extrapolations of the approach for compatibility with systems-on-a-chip, processing-in-memory, and reconfigurable logic where additional power saving approaches can be brought into play.

Sponsor: The Power Aware Computing/Communication (PACC) Program of the DARPA ITO Office

Principal Investigators:

• Peter Kogge, Vincent Freeh, Jay Brockman: CSE Dept. Univ. of Notre Dame
• Kanad Ghose: CS Dept., State Univ. of New York at Binghamton
• Benny Toomarian: Center for Integrated Space MicroElectronics, NASA JPL

Some recent posters and presentations

• Project Kickoff Scottsdale, AZ
• PACC Program Review Nov. 2000, Annapolis, MD
• Poster November 2000 PI Meeting

Some recent Morph papers

• Peter M. Kogge, Jeffrey Nankung, Nazeeh Aranki, N. Benny Toomarian, Kanad Ghose, "Characterization of Future Deep Space Computing Loads," Space Mission Challenges for Information Technology (SMC-IT)," Pasadena, CA, July, 2003.
• "Energy-Efficient Issue Queue Design" Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose, Peter Kogge, "Energy-Efficient Issue Queue Design", To appear in IEEE Transactions on Very Large Scale Integration Systems, 2003.
• Arun Rodrigues, "RuDRA: A Reactive Dissipation Reducing Architecture," M.S. Thesis, CSE Dept., Univ. of Notre Dame, April 28, 2003.
• Peter M. Kogge, Jeffrey Nankung, Nazeeh Aranki, N. Benny Toomarian, Kanad Ghose, "A Comparative Analysis of Power and Energy Management Techniques in Real Embedded Applications," IEEE Int. Workshop on Innovative Architectures (IWIA'03), Kauai, HI, Jan. 2003.
• Robert J. Minerick, "Feedback-Directed, Adaptive Energy Control," M.S. Thesis, CSE Dept., Univ. of Notre Dame, Nov. 2002.
• Robert J. Minerick, Vincent W. Freeh, and Peter M. Kogge, "Dynamic power management using feedback," Proc. of Workshop on Compilers and Operating Systems for Low Power, pp. 6-1--6-10, Charlottesville, Va, September, 2002.
• Oguz Ergin, Kanad Ghose, Gurhan Kucuk, Dmitry Ponomarev, "A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors," 20th IEEE International Conference on Computer Design (ICCD'02).
• Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose, "Energy-Efficient Design of the Reorder Buffer" 12th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'02), Seville, Spain, September 2002. Published as Lecture Notes in Computer Science, LNCS 2451, pp.289-299.2) , Freiburg, Germany, September 2002, pp.118-121.
• Gurhan Kucuk, Dmitry Ponomarev, Kanad Ghose, "Low-Complexity Reorder Buffer Architecture," 16th ACM International Conference on Supercomputing (ICS'02), New York, June 2002, pp. 57-66.
• Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose, "AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors," in 5th Design, Automation and Test in Europe Conference (DATE'02), Paris, France, March 2002, pp. 124-129.
• Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose, "Reducing Power Requirements of Instruction Scheduling Through Dynamic Allocation of Multiple Datapath Resources," ACM 34-th Symp. on Microarchitecture (MICRO-34), Dallas, TX, Dec. 2001, pp.90-101
• Gurhan Kucuk, Kanad Ghose, Dmitry Ponomarev, Peter Kogge, "Energy Efficient Instruction Dispatch Buffer Design for Superscalar Instruction Dispatch Buffer Design for Superscalar Processors," Proc. ACM Int. Symp. on Low Power Electronics and Design (ISLPED01), Long Beach, CA, Aug. 2001, pp. 237-243.
• Michael G. Kirkpatrick Vincent W. Freeh Peter M. Kogge Robert J. Minerick, "Exploiting Morphable Microarchitectures for Saving Energy," Univ. of Notre Dame CSE Dept. Tech. Report, 0109, Aug. 22, 2001.
• Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose, " Dynamic Allocation of Datapath Resources for Low Power," Workshop on Complexity-Effective Design (WCED'01), 28th International Symposium on Computer Architecture (ISCA-28), Goteborg, Sweden, June 2001.
• Zawodny, Jason and Peter M. Kogge, "Cache In Memory," International Workshop on Innovative Architecture 2001 (IWIA01), Maui High Performance Computer Center, Maui, HI, Jan. 18-19, 2001.
• Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose, "Power Reduction in Superscalar Datapaths through dynamic bit-slice Activation," International Workshop "Innovative Architecture for Future Generation High-Performance Processors and Systems" (IWIA'01), 2001, pp.16-24.
• Kogge, Peter M., Vincent W. Freeh, Kanad Ghose, Nikzad Toomarian, Nazeeh Aranki, "Morph: Adding an Energy Gear to a High Performance Microarchitecture for Embedded Applications," Kool Chips Workshop, MICRO-33, Monterey, CA, Dec. 10, 2000
• Ghose, Kanad, Dmitry Ponomarev, Gurhan Kuck, Andrew Flinders, Peter M. Kogge, "Exploiting Bit-Slice Inactivities for Reducing Energy Requirements of Superscalar Processors," Kool Chips Workshop, MICRO-33, Monterey, CA, Dec. 10, 2000.
• Kanad Ghose, " "Reducing Energy Requirements for Instruction Issue and Dispatch in Superscalar Microprocessors," Int. Symp. on Low Power Electronics and Design (ISLPED'00), July 2000, pp.231-234.

Some working reports

• Virgil Andronache, Variable Configuration Memory Cost Analysis, Nov. 28, 2001.

Some key background papers:

• Gang Quan and Sharon Hu, "Energy Efficient Fixed-Priority Scheduling for Real-Time Systems on Variable Voltage Processors," Best Paper Award Design Automation Conference, June 2001
• Zyuban, Victor and Peter M. Kogge, "Inherently Lower-Power High-Performance Superscalar Architectures," IEEE Trans. on Computers, March, 2001, (Vol. 50, No. 3). pp. 268-285.
• Zyuban, Victor and Peter M. Kogge, "Optimization of High-Performance Super-Scalar Architectures for Energy-Delay Product," ACM/IEEE International Symposium on Low Power Electronics and Design, July 2000, Portofino, Italy
• Zyuban, Victor, "Inherently Lower Power High Performance Superscalar Architectures," Ph. D. Thesis, CSE Dept., Univ. of Notre Dame, March 2000.
• Zyuban, Victor and Peter M. Kogge, "Application of STD Method to Latch Power Estimates," IEEE Trans. on VLSI Systems, Vol. 7, No. 1, March 1999, pp.111-115.
• Zyuban, Victor and Peter M. Kogge, "The Energy Complexity of Register Files," Int. Symp. on Low-Power Electronics and Design, Monterey, CA, Aug. 10-13, 1998, pp.305-310.
• Kanad Ghose and Milind B. Kamble, "Reducing Power in Superscalar Processor Caches Using Subbanking, Multiple Line Buffers and Bit-Line Segmentation," Int.l Symp. on Low Power Electronics and Design (ISLPED'99), August 1999, pp.70-75.
• Milind B. Kamble and Kanad Ghose, "Analytical Energy Dissipation Models For Low Power Caches," Int. Symp. on Low Power Electronics and Design (ISLPED'97), August 1997, pp.343-348.

Last updated 1/15/04

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